Logic AggreGATE from Aptix Corporation (block-based prototyping methodology)
Platforms: Solaris, HP-UX
Price: pricing begins under $50,000
URL: http://www.aptix.com
EDA tool that implement the Aptix's block-based prototyping methodology. Logic AggreGATEr enables the interactive mapping of system-on-chip (SoC) ASIC designs into Aptix System Explorer family of reconfigurable prototyping systems.

Logic AggreGATEr provides the key link between the CAE design creation environment and the prototyping system. It takes system level Verilog, EDIF or XNF design netlists and allows users to interactively move design blocks into bins representing prototyping components. IP blocks and system level components can be treated as `black boxes` so they are easily assigned to distinct component modules in the prototyping system. The various design blocks of the SoC ASIC custom logic, represented in the prototype in FPGAs, are interactively grouped into bins representing the FPGAs, keeping track of the number of gates and pins utilized. Once the user has grouped the performance-critical blocks, Logic AggreGATEr can automatically group the remaining logic. The Logic AggreGATEr output is a set of netlists representing the system level topology and each FPGA used in the prototype. These netlists are ready for importation into the System Explorer environment.

The block-based prototyping methodology of the Logic AggreGATEr provides a mechanism to map and verify individual design blocks incrementally and in parallel with the design creation process. This shortens the `net` prototype creation time to achieve real-world prototype operation to only the few days required to map and verify the last RTL block designed.

Users also benefit from the efficiency of IP design reuse for system-on-a-chip ASICs. IP blocks can be prototyped as black-box `hard IP` in bonded out silicon or off-the-shelf components, or `soft IP` prototyped in user designated FPGAs. Debugging designs is simple because the mapping process is both under the users interactive control and follows the natural hierarchy of the design. This also makes tracing design problems back to the source netlist an intuitive process.

Logic AggreGATEr's mapping process is quick and easy compared to the time consuming, counter-intuitive partitioning processes of `mainframe` ASIC emulators, which flatten a design's natural block-based hierarchy and therefore, make debugging and design iterations difficult and time consuming.

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