Design teams, not single engineers, will create multi-million gate programmable logic designs. To facilitate this, Quartus utilizes a centralized object-oriented database, which can be accessed by multiple engineers across a network. To keep track of the many design changes typical of system-level designs, Quartus will come standard with integration into popular revision control systems such as RCS, SCCS, and PVCS. Alternatively, engineers will be able to integrate their own revision control systems.
As designs increase in size, so too does the time it takes to compile a design. Multi-million-gate designs in ASICs typically take days to place and route. To resolve this problem, Altera has created the nSTEP Compiler to minimize compilation times by providing multiprocessor support and true incremental compilation. After a design has been compiled once, any incremental change to the design requires only re-synthesis and re-placement of the affected logic area, reducing compilation time by up to 90 percent.
Return to product index