Another new product, TurboCheck, offers both gate and RTL test analysis. TurboCheck-RTL identifies testability problems early in the design cycle. Removing these problems at the RTL stage improves test insertion, Automatic Test Pattern Generation (ATPG), and fault coverage. Using Turbocheck-Gate or TurboCheck-RTL helps reduce design iterations. TurboCheck-RTL checks Verilog RTL designs before synthesis and verification. TurboCheck-Gate is used after synthesis.
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